Integrated circuits are made up of millions of active devices formed in or on a substrate, such as a silicon wafer. The active devices are chemically and physically connected into a substrate and are interconnected through the use of multilevel interconnects to form functional circuits. Typical multilevel interconnects comprise a first metal layer, an interlevel dielectric layer, and sometimes a third and subsequent metal layers. Interlevel dielectrics, such as doped and undoped silicon dioxide (SiO2) and/or low-κ dielectrics, are used to electrically isolate the different metal layers. As each layer is formed, typically the layer is planarized to enable subsequent layers to be formed on top of the newly formed layer.
Metals such as tungsten and copper are increasingly being used as conductive materials to form the interconnections in integrated circuit devices. One way to fabricate planar metal circuit traces on a silicon dioxide substrate is referred to as the damascene process. In accordance with this process, the silicon dioxide dielectric surface is patterned by a conventional dry etch process to form holes and trenches for vertical and horizontal interconnects. The horizontal interconnects define the circuit patterns on each level of the device and are interconnected by way of vertical interconnects, known as vias. The patterned surface is coated with an adhesion-promoting layer such as titanium or tantalum and/or a diffusion barrier layer such as titanium nitride or tantalum nitride. The adhesion-promoting layer and/or the diffusion barrier layer are then over-coated with a tungsten or copper layer. Chemical-mechanical polishing is employed to reduce the thickness of the tungsten or copper over-layer, as well as the thickness of any adhesion-promoting layer and/or diffusion barrier layer, until a planar surface that exposes elevated portions of the silicon dioxide surface is obtained. The vias and trenches remain filled with electrically conductive tungsten or copper forming the circuit interconnects.
Another use of the damascene process is in the formation of chip interconnects using polysilicon plugs. To form polysilicon plugs, a hole is etched into an insulating layer, such as silicon dioxide. Next, polysilicon is deposited into the hole. The polysilicon on the surface of the oxide is then planarized using chemical-mechanical polishing or reactive-ion etching. A metal line subsequently may be used to interconnect selected polysilicon plugs by a damascene process as described herein.
Compositions and methods for planarizing or polishing the surface of a substrate, especially for chemical-mechanical polishing (CMP), are well known in the art. Polishing compositions (also known as polishing slurries) typically contain an abrasive material in an aqueous solution and are applied to a surface by contacting the surface with a polishing pad saturated with the polishing composition. The polishing compositions typically comprise chemical reagents that react with the surface of a substrate being polished in order to convert the surface into a softer, more readily abradable form. The abrasive material in conjunction with the polishing pad (e.g., polishing cloth or disk) removes material from the substrate surface via mechanical action.
One of the challenges in development of improved CMP processes is control of dishing, also known as recessing. Dishing refers to the deviation from planarity of material resident in the individual device features (e.g., lines or vias). In order to ensure adequate planarization of a substrate surface and to ensure complete removal of metal or polysilicon present outside of the device features, a certain amount of polishing beyond that necessary to achieve coplanarity of the device feature with the substrate surface, i.e., overpolishing, is typically necessary. Metal or polysilicon residing within device features is subject to attack by chemical components of the polishing composition as well as to mechanical abrasion by abrasive particles in the polishing composition. The chemistry of polishing compositions often can be tailored to minimize chemical attack on materials residing in device features. However, the abrasive particles commonly used in CMP compositions typically have particle sizes that are smaller than the feature dimensions, and thus materials residing in device features are accessible to the abrasive particles and are thus subject to mechanical abrasion during overpolishing, with resulting dishing of the device features.
Attempts have been made to control dishing through incorporation of various surface-active agents into polishing compositions that interact with the surface of materials residing in device features and provide a steric barrier to the approach of abrasive particles. However, the surface-active agents also reduce the removal rate of metals or polysilicon residing outside of the device features. Mechanical approaches to control dishing include reduction of downforce pressure of the substrate to be polished against the polishing pad during overpolishing. However, reducing the downforce increases the amount of time required for adequate polishing, which reduces device throughput and increases overall cost. Thus, there remains a need in the art for improved polishing compositions and methods for the chemical-mechanical planarization of substrates having device features thereon, such as lines, vias, and plugs.
The invention provides such a polishing composition and method.